The invention relates to link list buffer architectures, for example for use in high performance switches.
A critical parameter in high performance switches for computer buses, such as PCI Express and Infiniband, is the underlying buffer architecture.
In an input-output buffer architecture, packets are sorted and stored in partitions of the output buffer, according to their destination. Packets to different destinations can therefore be independently forwarded, even when the buffers are implemented with pure First In First Out (FIFO) storage elements. An input-output buffer architecture can be implemented using storage elements such as FIFOs that are easy to handle, and can provide independence between packet streams at the cost of increased buffer space.
A Virtual Output Queue (VOQ) buffer architecture, on the other hand, uses just one buffer. Independence between packet streams can be provided by using a random access memory. (RAM) storage element for implementing the buffer. As any entry of a RAM can be freely accessed, packets to different destinations can be independently forwarded directly from the buffer, without the need for a costly output buffer. A conventional VOQ buffer architecture, however, causes problems in the case of high performance switches in which packets may be received every cycle. Specifically, when the packet is stored, both the entry for the packet itself and an entry for a pointer to it need to be written at the same time. As the addresses of these two entries are not the same, they will either have to be written in two cycles, or a RAM with more than one write port must be used and RAMs with more than one read and one write port are either costly in terms of size, or not available for all technologies.
The present invention seeks to provide an improved buffer architecture.